1. Field of the Invention
This invention relates to circuits and methods for detection of the magnitude of input analog voltage signals and the conversion of the detected magnitude to a digital code. More particularly, this invention relates to multiple stage analog-to-digital converters where a first conversion determines a coarse range of the input analog voltage signal and subsequent conversions resolve the determination of input analog voltage signal to finer increments.
2. Description of Related Art
Analog-to-digital (A/D) converters are well known in the art for the conversion of continuously variable electronic signals to digital codes representing the magnitude of the electronic signals. Two types of A/D converters include the Successive Approximation type A/D converter and the FLASH type A/D converter. The Successive Approximation type A/D converter functions by creating a trial digital code and converting the trial digital code to a trial analog signal, the trial analog signal is compared to the input signal and an error signal is generated. A new digital code is created. The digital new code is converted to a new trial analog signal. The new trial analog signal is compared to the input signal and a new error signal is created. Then a new digital code is created. This process is successively repeated until the error signal approaches a zero level and the correct digital code has been generated to represent the input signal.
The FLASH A/D converter, as shown in FIG. 1, has a sample and hold circuit 10 to capture and retain the analog input signal VIN 5. The sampled and held analog input signal 45 is the input to multiple voltage comparators 30a, 30b, . . . , 30n-1, 30n. The number of voltage comparators 30a, 30b, 30n-1, 30n is determined as: EQU N.sub.c =2.sup.n
where: PA1 where: PA1 where: PA1 where: PA1 where:
Nc is the number of voltage comparators 30a, 30b, . . . , 30n-1, 30n, and PA2 N is the number of binary digits of the digital code D0, D1, . . . , DN-2, DN-1, 40. PA2 .DELTA.V.sub.MSB is the increment between each coarse reference voltage, PA2 n.sub.MSB is the number of Most Significant Bits (MSB) of the digital code D0, D1, . . . , Dn-2, Dn-1 175. PA2 .DELTA.V.sub.LSB is the increment between each coarse reference voltage, PA2 n.sub.LSB is the number of Most Significant Bits (MSB) of the digital code D0, D1, . . . , Dn-2, Dn-1 175. PA2 N.sub.cc is the number of coarse converter, and PA2 n.sub.MSB is the number of Most Significant Bits. PA2 N.sub.FC is the number of fine converters, and PA2 n.sub.MSB is the number of Least Significant Bits.
Further, each voltage comparator has a voltage reference 17a, 17b, . . . , 17n-1, 17n. The voltage references 17a, 17b, . . . , 17n-1, 17n are generated in the voltage reference generator 15. The voltage reference generator 15 is classically a resistive voltage divider connected between the top reference voltage VRT 20 and the bottom reference voltage VRB 25. Each of the voltage references 17a, 17b, . . . , 17n-1, 17n are spaced incrementally between the top reference voltage VRT 20 and the bottom reference voltage VRB 25.
The outputs 32a, 32b, . . . , 32n-1, 32n of the voltage comparators 30a, 30b, . . . , 30n-1, 30n form a thermometer code. The thermometer code has a first logic level such as a "1" for those comparators 30a, 30b, . . . , 30n-1, 30n where the voltage references 17a, 17b, . . . , 17n-1, 17n are less than the amplitude of the sampled and held analog input signal 45 and a second logic level such as a "0" for those comparators where the voltage references 17a, 17b, . . . , 17n-1, 17n are greater than the sampled and held analog input signal 45.
The outputs 32a, 32b, 32n-1, 32n of the comparators 30a, 30b, . . . , 30n-1, 30n are the inputs to the encoder 35. The encoder 35 creates the digital code D0, D1, . . . , Dn-1, Dn 40.
The structure of the FLASH A/D converter becomes very large and cumbersome as the number of binary digits of the digital code D0, D1, . . . , Dn-1, Dn 40 increases. For instance, if the digital code D0, D1, . . . , Dn-1, Dn 40 had eight binary digits, then there would be 2 or 256 comparator 30a, 30b, . . . , 30n-1, 30n and 256 voltage references 17a, 17b, . . . , 17n-1, 17n from the reference generator 15. However, if the digital code D0, D1, . . . , Dn-2, Dn-1 40 has twelve binary digits, there are 2.sup.12 or 4096 comparators 30a, 30b, . . . , 30n-1, 30n and 4096 voltage references 17a, 17b, . . . , 17n-1, 17n from the voltage reference generator 15. Thus, an increase in precision of the conversion, cause a significantly more complex designs.
To alleviate this complexity, multiple stage A/D converters have been disclosed in U.S. Pat. No. 4,903,028 (Fukushima), U.S. Patent 5,291,198 (Dingwall et al.), and U.S. Pat. No. 5,726,653 (Hsu et al.), and are shown in FIG. 2. The analog input signal VIN 105 is the input to the sample and hold circuit 110. The sample and hold circuit 110 periodically samples and retains the analog VIN 105 to create the sampled and held analog input signal 140.
The sampled and held analog input signal 140 is the input to a set of coarse voltage comparators 160. The coarse voltage comparators 150 compare the sampled and held analog input signal 140 to a set of coarse reference voltages 125. The results of the comparison of the sampled and held analog input signal 140 and the set of coarse reference voltages 125 is a set of coarse thermometer codes 160 indicating the amplitude of the sampled and held analog input signal 140 relative to the each of the set of coarse reference voltages.
The set of coarse thermometer codes 160 has the first logic level (1) at those comparators of the set of coarse comparators 150 that have a coarse reference voltage from the set of coarse reference voltages 125 that is less than the amplitude of the sampled and held analog input signal 140, and have the second logic level (0) for those comparators of the set of coarse comparators 150 that have a coarse reference voltage from the set of coarse reference voltages 125 that is greater than the amplitude of the sampled and held analog input signal 140.
The coarse reference voltages 125 are generated by the voltage reference generator 115. The voltage reference generator is connected between the top reference voltage source VRT 120 and the bottom reference voltage source VRB 115. Each coarse reference voltage of the set of coarse reference voltages 125 is distributed incrementally between the top reference voltage source VRT 120 and the bottom reference voltage source 125. The coarse voltage increment between each coarse reference voltage is determined as: ##EQU1##
A sub-set of fine reference voltages are placed between each of the coarse reference voltages. The fine voltage increment between each fine reference voltage is: ##EQU2##
All of the subsets of the fine reference voltages 130 are transferred to the steering/select logic 135. The steering/select logic 135 decodes the coarse thermometer code 160 to determine the two coarse voltage references that the sampled and held analog input voltage 140 lies between. That subset of the fine reference voltages between two coarse voltage references forms the one set of fine reference voltages connected to the fine comparators 155.
The sampled and held analog input signal 140 is connected to the fine comparators and is compared to each of the fine reference voltages of the set of fine reference voltages 145. The results of comparison of sampled and held analog input signal 140 with each of the fine reference voltages 145 are the set of fine thermometer codes 165.
The set of fine thermometer codes 165 has a first logic level (1) at those comparators of the set of fine comparators 155 that have a fine reference voltage of the set of fine reference voltages 145 that is less than or equal to the amplitude of the sampled and held analog input signal 140, and has the second logic level (0) for those comparators of the set of fine comparators 155 that have a fine reference voltage of the set of fine reference voltages 145 that is greater than the amplitude of the sampled and held analog input signal 140.
The coarse thermometer codes 160 and the fine thermometer codes 165 are transformed in the encoder 170 to the digital code D0, D1, . . . , Dn-2, Dn-1 175.
The digital code D0, D1, . . . , Dn-2, Dn-1 175 is composed of the Least Significant Bits (LSB) and the Most Significant Bits (MSB) appended together. The number of coarse converters is determined as: EQU Ncc=2.sup.n.sup..sub.MSB
The number of fine converters is determined as: EQU N.sub.FC =2.sup.n.sup..sub.LSB
If the number of bits in the digital code D0, D1, . . . , Dn-2, Dn-1 175 is twelve as above described, but the number of Most Significant Bits and the number of Least Significant Bits is six each, then the number of comparators (Nc) is now. EQU N.sub.c =N.sub.cc +NFC EQU N.sub.c =2.sup.6 +2.sup.6 =128.
The FLASH A/D converter described in FIG. 1 would have had 4096 comparators while the comparator of FIG. 2 has 128 comparators. This is a significant reduction in complexity with only the addition of the steering/select logic 135.
The voltage reference generators 115 still has 4096 voltage taps and with the addition of the connections for the steering/select logic 135 has additional complexity.
The coarse comparators 150 and the fine comparators 155 are generally implemented as differential amplifiers. The differential amplifier is well known in the art. The reference voltage is usually connected to the noninverting input terminal while the analog input voltage is connected to the inverting input terminal. The output terminal has the first logic level (1) for any voltage less than the reference voltage and has the second logic level (0) for any voltage greater than the reference voltage.
U.S. Pat. No. 5,355,135 (Redfern) describes a semi-flash A/D converter using a reduced number of comparators and a voltage comparator which can be used in a semi-flash mode of operation to obtain both the Most Significant Bits and the Least Significant Bits for a digital conversion. A feature of Redfern is a 6 input switched capacitor comparator for use in accomplishing a semi-flash conversion of an analog signal to a digital signal. A Most Significant Bit and a Least Significant Bit are sequentially obtained using a single comparator comprising a 6-input switched capacitor operational amplifier. Three inputs are switchably and capacitively coupled to the amplifier input through a first capacitor, and three inputs are switchably and capacitively coupled to the amplifier input through a second capacitor. The input terminal of the amplifier acts as a virtual ground in which charges simultaneously coupled thereto are summed, and charges subsequently applied are subtracted. The capacitors function as a sample-and-hold network is retaining the input signal for both the Most Significant Bit and Least Significant Bit comparisons.
U.S. Pat. No. 4,507,649 (Dingwall et al.) teaches a FLASH A/D converter that limits the amount of charge that can be displaced on any given summing capacitor via the signal input bus and by isolating each of the signal input switches from the signal input bus by respective serial impedances. A field effect transistor (FET) is connected between each signal input switch and the signal input bus. The gate electrodes of the FET's are biased at DC potentials, which are tailored to the relative position of the respective FET's along the resistive ladder. The FET's are constrained to operate in the source follower mode for certain ranges of the input signal so that the individual summing capacitors cannot charge or discharge to a potential exceeding the respective FET gate potential minus the threshold potential of the transistor. This reduces loading on the resistive ladder. The drain-source impedance of the respective FET's shields the signal input bus from clock feed-through attendant the signal input switches.
U.S. Pat. No. 4,922,252 (Draxelmayr et al.) discloses an A/D converter operating on the principle of charge distribution. The A/D converter includes a capacitor network having dual-weighted capacitors including two smallest capacitors. The capacitors each have two terminals. A comparator has a first input connected to one of the terminals of each of the capacitors and a second input and a reference switch is connected between each of the one terminals and a first reference potential. Other switches each selectively connect the other of the terminals of a respective one of the capacitors to an input analog potential, the first reference potential and a second reference potential. A coupling capacitor is connected upstream of the first input of the comparator.
U.S. Pat. No. 4,639,715 (Doluca) describes an improved A/D converter in which the polarity of the input range is selectable independent of the polarities of the reference inputs. The A/D converter circuit uses the same flash converter circuit to generate both the high order and low order bits of the digital output code. After the flash converter circuit generates the high order bits, an equivalent analog voltage of the high order bits is subtracted from the analog input signal to produce a residual signal. This residual signal is multiplied by a factor corresponding to the number of bit positions of the high order bits to produce a product signal. The product signal is reapplied to the flash converter circuit, which then generates the low order bits. Because the same flash converter circuit is used to generate both the high and low order bits, a significant reduction in the size of an analog to digital converter circuit can be achieved. Another aspect of Doluca is that the polarities of the full scale input and the low scale input are programmable to be the same as or the opposite of the reference inputs. In the illustrated embodiment, the converter circuit includes a switched input comparator array in which the order in which a reference signal and an input signal are inputted by the array is a function of the polarity of one of the reference inputs, and the correspondence between the reference input polarity and the desired input range polarity. This changes the input order of the input signal and the reference signal allow the polarity of the full scale analog input signal (and the low scale input signal) to be set independently of the polarity of the reference inputs. Consequently, the converter circuit does not require particular reference input polarities in order to achieve the desired input range polarities.
U.S. Pat. No. 4,523,107 (Peterson) discloses a switched capacitor comparator. The intent of Peterson is to provide a switched capacitor comparator having improved noise rejection and reduced offset voltage.
Further, the switched capacitor comparator of Peterson has accurate gain and improved stability over temperature with higher speed and resolution. The switched capacitor comparator of Peterson is comprised of a plurality of capacitively coupled amplifier or gain stages. Some or all of the amplifiers or gain stages have differential inputs coupled to a reference voltage. Each gain stage has a switch coupled between its output and its input to provide feedback. The switches are sequentially switched to reduce offset. Further, some or all of the switches have feedback capacitors placed in parallel with the switches to provide accurate gain and stability.